The reduction in memory cell and other circuit feature sizes for high density dynamic random access memories (DRAMs) and other circuitry is a continuing goal in semiconductor fabrication. DRAM devices comprise arrays of memory cells each of which contains an access transistor and a capacitor. Areas within a DRAM in which electrical connections are made (i.e. between the capacitors and transistors) are generally referred to as active areas. The active areas within a memory array typically weave across the array in a serpentine manner in a substantially horizontal direction (see FIG. 2). Bit lines within the array typically also weave horizontally across the array in an opposing serpentine manner relative to the active areas, with wordlines of the array running substantially orthogonally relative to the active areas and bitlines.
In conventional memory cell and DRAM construction, capacitors are typically formed to conform to the serpentine weave of the active regions. Masking and etching processes for producing such conventional capacitor constructions can be problematic, especially at the minimum photolithographic dimensions for high density DRAM arrays. Accordingly, it is desirable to develop alternative capacitor constructions and methodology for production of alternative capacitor constructions.